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1 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a bicmos lvpecl clock generator ? device specification sonet/sdh/atm oc-12 transmitter and receiver s3067 features ? sige bicmos technology ? complies with bellcore and itu-t specifications ? on-chip high-frequency pll for clock generation ? supports: - oc-48 (with fec) - oc-24 (with fec) - oc-12 (with fec) - oc-3 (with fec) - fibre channel ? fec capability up to 8 bytes per 255-byte block ? reference frequency C 131.25 mhz to 178 mhz ? interface to lvpecl and ttl logic ? 16-bit single-ended lvpecl data path ? compact 156 pin tbga package ? diagnostic loopback mode ? supports line timing ? lock detect ? signal detect input ? low jitter lvpecl interface ? internal fifo to decouple transmit clocks ? single 3.3 v supply ? typical power 1.5 w applications ? wavelength division multiplexing equipment ? sonet/sdh-based transmission systems ? sonet/sdh modules ? sonet/sdh test equipment figure 1. system block diagram multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec s3067 ? atm over sonet/sdh ? section repeaters ? add drop multiplexers (adm) ? broad-band cross-connects ? fiber optic terminators ? fiber optic test equipment general description the s3067 sonet/sdh transceiver chip is a fully integrated multirate serialization/deserialization so- net oc-48, oc-24, oc-12 and oc-3 interface device. the chip performs all necessary serial-to- parallel and parallel-to-serial functions in conformance with sonet/sdh transmission and forward error correction (fec) standards. the de- vice is suitable for sonet-based wdm applications. figure 1 shows a typical network application. on-chip clock synthesis is performed by the high- frequency phase-locked loop on the s3067 transceiver chip allowing the use of a slower external transmit clock reference. the chip can be used with a 131.25 mhz to 178 mhz reference clock in support of existing system clocking schemes. the low jitter lvpecl interface guarantees compli- ance with the bit-error rate requirements of the bellcore and itu-t standards. the s3067 is pack- aged in a 156 pin tbga, offering designers a small package outline. the s3067 supports fec designs with internal divid- ers or external clocking modes. s3076 clock recovery unit s3062 receive s3062 transmit fec added s3067 receive deserialization s3076 clock recovery unit s3062 receive fec data stripped off s3062 transmit s3067 receive deserialization 2.488 gbps x 2.488 gbps 155 mbps xx 2.67 gbps x + y 167 mbps x + y 167 mbps x + y 155 mbps x x + y 2.67 gbps 2.488 gbps x performance monitor performance monitor x = data y = fec data e/o o/e optical fiber s3067 transmit serialization s3067 transmit serialization
2 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a sonet overview synchronous optical network (sonet) is a stan- dard for connecting one fiber system to another at the optical level. sonet, together with the synchro- nous digital hierarchy (sdh) administered by the itu-t, forms a single international standard for fiber interconnect between telephone networks of differ- ent countries. sonet is capable of accommodating a variety of transmission rates and applications. the sonet standard is a layered protocol with four separate layers defined. these are: ? photonic ? section ? line ? path figure 2 shows the layers and their functions. each of the layers has overhead bandwidth dedicated to administration and maintenance. the photonic layer simply handles the conversion from electrical to op- tical and back with no overhead. it is responsible for transmitting the electrical signals in optical form over the physical media. the section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. key functions of this layer are framing, scrambling, and error monitoring. the line layer is responsible for the reliable transmission of the path layer informa- tion stream, carrying voice, data, and video signals. its main functions are synchronization, multiplexing, and reliable transport. the path layer is responsible for the actual transport of services at the appropri- ate signaling rates. data rates and signal hierarchy table 1 contains the data rates and signal designa- tions of the sonet hierarchy. the lowest level is the basic sonet signal referred to as the synchronous transport signal level-1 (sts-1). an sts- n signal is made up of n -byte-interleaved sts-1 signals. the op- tical counterpart of each sts- n signal is an optical carrier level- n signal (oc- n ). the s3067 chip sup- ports up to the oc-48 rate with different fec modes. frame and byte boundary detection the sonet/sdh fundamental frame format for sts-48 consists of 144 transport overhead bytes followed by synchronous payload envelope (spe) bytes. this pattern of 144 overhead and 4176 spe bytes is repeated nine times in each frame. frame and byte boundaries are detected using the a1 and a2 bytes found in the transport overhead. (see figure 3.) for more details on sonet operations, refer to the bellcore sonet standard document. elec. ccitt optical data rate (mbps) sts-1 oc-1 51.84 sts-3 stm-1 oc-3 155.52 sts-12 stm-4 oc-12 622.08 sts-24 stm-8 oc-24 1244.16 sts-48 stm-16 oc-48 2488.32 table 1. sonet signal hierarchy figure 2. sonet structure figure 3. stsC48/ocC48 frame format 9 rows 48 a1 bytes 48 a2 bytes a1 a1 a1 a1 a2 a2 a2 a2 transport overhead 144 columns 144 x 9 = 1296 bytes synchronous payload envelope 4176 columns 4176 x 9 = 37,584 bytes 125 sec s s end equipment payload to spe mapping maintenance, protection, switching optical transmission scrambling, framing fiber cable end equipment section layer photonic layer line layer path layer path layer section layer photonic layer line layer functions
3 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a s3067 overview the s3067 transceiver implements sonet/sdh and wdm serialization/deserialization, and transmis- sion functions. the block diagram in figure 4 shows the basic operation of the chip. this chip can be used to implement the front end of wdm equipment, which consists primarily of the serial transmit inter- face and the serial receive interface. the chip handles all the functions of these two ele ments, in- cluding parallel-to-serial and serial-to-parallel conversion, clock generation, and system timing. the system timing circuitry consists of management of the data stream and clock distribution throughout the front end. s3067 has the ability to bypass the internal vco with an external source and also with the receive clock. the device generates 14/15, 15/14, 16/17 and 17/16 clocks based upon the received clock and an external clock to incorporate the fec capability. the dividers support the first two rates shown in table 4. the s3067 is divided into a transmitter section and a receiver section. the sequence of operations is as follows: 0 l e s e t a r1 l e s e t a re d o m g n i t a r e p o 00 3 - c o 01 2 1 - c o 10 c f / e b g / 4 2 - c o 11 8 4 - c o table 2. data rate select transmitter operations: 1. 16-bit parallel input 2. parallel-to-serial conversion 3. serial output receiver operations: 1. serial input 2. serial-to-parallel conversion 3. 16-bit parallel output internal clocking and control functions are transpar- ent to the user. s3067 supports six different code rates, besides the normal rate, for each of the four operating modes. y t i l i b a p a c g n i t c e r r o c r o r r e g n i w o h s e t a r e d o c e u d n o i s n a p x e h t d i w d n a b b s f & s d r o w e d o c o t k c o l c t u p n i d e s a e r c n i f o e l p m a x e ) z h m ( 6 1 - m t s / 8 4 - s t s r o f y c n e u q e r f k c o l b e t y b - 5 5 2 r e p s e t y b 8e s a e r c n i % 4 1 . 7 = 8 3 2 / 5 5 2 3 6 . 6 6 1 = 4 1 / 5 1 * 2 5 . 5 5 1 = 8 3 2 / 5 5 2 * 2 5 . 5 5 1 k c o l b e t y b - 5 5 2 r e p s e t y b 7e s a e r c n i % 5 2 . 6 = 0 4 2 / 5 5 2 4 2 . 5 6 1 = 6 1 / 7 1 * 2 5 . 5 5 1 = 0 4 2 / 5 5 2 * 2 5 . 5 5 1 k c o l b e t y b - 5 5 2 r e p s e t y b 6e s a e r c n i % 7 3 . 5 = 2 4 2 / 5 5 27 8 . 3 6 1 = 2 4 2 / 5 5 2 * 2 5 . 5 5 1 k c o l b e t y b - 5 5 2 r e p s e t y b 5e s a e r c n i % 1 5 . 4 = 4 4 2 / 5 5 23 5 . 2 6 1 = 4 4 2 / 5 5 2 * 2 5 . 5 5 1 k c o l b e t y b - 5 5 2 r e p s e t y b 4e s a e r c n i % 6 6 . 3 = 6 4 2 / 5 5 2 1 2 . 1 6 1 = 2 8 / 5 8 * 2 5 . 5 5 1 = 6 4 2 / 5 5 2 * 2 5 . 5 5 1 k c o l b e t y b - 5 5 2 r e p s e t y b 3e s a e r c n i % 2 8 . 2 = 8 4 2 / 5 5 21 9 . 9 5 1 = 8 4 2 / 5 5 2 * 2 5 . 5 5 1 table 4. fec modes table 3. fec select 0 c e f12 o c v r e d i v i d k l c s r r e d i v i d 001 7 16 1 101 6 17 1 011 5 14 1 111 4 15 1 000 7 1x 100 6 1x 010 5 1x 110 4 1x c c m a6 7 0 3 se c i v e d y r e v o c e r k c o l c 8 4 - c o c c m a2 6 0 3 sr o t i n o m e c n a m r o f r e p 8 4 - c o suggested interface devices
4 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 4. s3067 transceiver functional block diagram clocks lockdet 155mckp/n 19mck pclkp/n pherr tsdp/n tsclkp/n ovref pout[15:0] poclkp/n timgen 16:1 parallel to serial clock synthesizer d txdp/n txclkp/n poclk (internal) refclkp/n piclkp/n txdp/n (internal) txclkp/n (internal) rsclkp/n dleb squelch ivref rstb sdlvpecl sdttl rsdp/n killrxclk lleb pin[15:0] bypass testen cap2 cap1 rlptime fecsel2 phinit d d d 1:16 serial to parallel timgen r 3 16 16 ratesel[0:1] fecsel[2:0] bypassclkp/n n slptime vco clock tx rx 2
5 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 5. clock synthesizer m n pd lpf vco vcoclk refclk fecsel (0-1) fecsel 2 rsclk where n = 14/15/16/17 m = 14/15/16/17 rsclk n vcoclk m rsclk divider vco divider = a high on fecsel2 selects rsclk divided by n. a low on fecsel2 selects the refclk. the refclk or rsclk divided by n is divided by 1/m (multiplied by m) in the loop. the value of m and n can be selected by fecsel0 and fecsel1. when fecsel2 = 0, vcoclk = refclk * m. the user must select the proper value of refclk and m to get the desired vcoclk frequency. when fecsel2 = 1, vcoclk = (rsclk * m) ? n. the user must select the proper m/n ratio (with fecsel0 and fecsel1) to get the desired vcoclk value. (see tables 3 and 4.) example: oc-48 fec capability of 8 bytes per 255-byte block. required vcoclk = 2.6656 ghz. method 1: required vcoclk = 2.6656 ghz fecsel2 = 0, selects refclk fecsel0 = 1 and fecsel1 = 0, selects vco divider(m) = 16 refclk = 2.6656 ghz ? 16 = 166.60 mhz vcoclk = refclk ? (1/m) = 166.60 * 16 = 2.6656 ghz method 2: required vcoclk = 2.6656 ghz fecsel2 = 1, selects rsclk fecsel0 = 0 and fecsel1 = 0, selects vco divider(m) = 17 and rsclk divider(n) = 16 rsclk = (2.6656 * 16) ? 17 = 2.5088 ghz vcoclk = rsclk ? n ? (1/m) = 2.5088 ghz ? 16 * 17 = 2.6656 ghz.
6 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a s3067 transceiver functional description transmitter operation the s3067 transceiver chip performs the serialization stage in the processing of a transmit sonet sts-48/ sts-24/sts-12/sts-3/gbe/fc data stream depend- ing on the data rate selected. it converts 16-bit parallel data to bit serial format. a high-frequency bit clock can be generated from a 131.25 mhz to 178 mhz frequency reference by us- ing an integral frequency synthesizer consisting of a phase-locked loop circuit with a divider in the loop. diagnostic loopback (transmitter to receiver) and line loopback (receiver to transmitter) is provided. see other operating modes . the bypass signal selects between the bypassclk and the vco clock. bypassclk can be used to pro- vide an alternative clock to the internal vco when the user selects an error correcting capability which is not provided by the s3067 dividers. the user must pro- vide the required frequency for the bypassclk when error-correcting capability of 6/5/4/3 bytes per 255-byte block is selected. clock synthesizer the clock synthesizer, shown in the block diagrams of figures 4 and 5, is a monolithic pll that gener- ates the serial output clock frequency locked to the input reference clock (refclkp/n). the refclkp/n input must be generated from a crystal oscillator that has a frequency accuracy bet- ter than the value stated in table 10 in order for the tsclk frequency to have the accuracy required for operation in a sonet system. lower-accuracy crys- tal oscillators may be used in applications less demanding than sonet/sdh. the on-chip pll consists of a phase detector, which compares the phase relationship between the vco output and the refclkp/n input, a loop filter which converts the phase detector output into a smooth dc voltage, and a vco, whose frequency is varied by this voltage. the divide by n and divide by m provide the counters required to support error correcting capabil- ity. the values of n and m can be selected by fecsel lines. the loop filter generates a vco control voltage based on the average dc level of the phase discrimi- nator output pulses. a single external clean-up capacitor is utilized as part of the loop filter. the loop filters corner frequency is optimized to minimize out- put phase jitter. timing generator the timing generation function, seen in figure 4, provides a divide-by-16 version of the transmit serial clock. this circuitry also provides an internally gen- erated load signal, which transfers the pin[15:0] data from the parallel input register to the serial shift register. the pclk output is a divide-by-16 rate version of transmit serial clock (divide-by-16). pclk is in- tended for use as a divide-by-16 clock for upstream multiplexing and overhead processing circuits. using pclk for upstream circuits will ensure a stable fre- quency and phase relationship between the data coming into and leaving the s3067 device. the timing generator also produces a feedback ref- erence clock to the clock synthesizer. a counter divides the synthesized clock down to the same fre- quency as the reference clock refclk. the pll in the clock synthesizer maintains the stability of the synthesized clock by comparing the phase of the internal clock with that of the reference clock (refclk). table 5. reference jitter limits e d o m g n i t a r e p oh t d i w d n a br e t t i j s m r 8 4 - s t sz h m 0 2 o t z h k 2 1c b d 1 6 - 4 2 - s t sz h m 0 1 o t z h k 2 1s p 2 2 1 - s t sz h m 5 o t z h k 2 1s p 4 3 - s t sz h m 1 o t z h k 2 1s p 6 1
7 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a parallel-to-serial converter the parallel-to-serial converter shown in figure 4 is comprised of a fifo and a parallel-to-serial register. the fifo input latches the data from the pin[15:0] bus on the rising edge of piclk. the parallel-to- serial register is a loadable shift register which takes its parallel input from the fifo output. an internally generated divide-by-16 clock, which is phase aligned to the transmit serial clock as de- scribed in the timing generator description, activates the parallel data transfer between registers. the serial data is shifted out of the parallel-to-serial register at the tsclk rate . fifo a fifo is added to decouple the internal and exter- nal (piclk) clocks. the internally generated divide-by-16 clock is used to clock out data from the fifo. phinit and lockdet are used to center or reset the fifo. the phinit and lockdet signals will center the fifo after the third piclk pulse. this is to insure that piclk is stable. this scheme allows the user to have an infinite pclk-to-piclk delay through the asic. once the fifo is centered, the pclk-to-piclk delay can have a maximum drift as specified in table 20. fifo initialization the fifo can be initialized in one of the following three ways: 1. during power up, once the pll has locked to the reference clock provided on the refclk pins, the lockdet will go active and initialize the fifo. 2. when rstb goes active, the entire chip is reset. this causes the pll to go out of lock and thus the lockdet goes inactive. when the pll re- acquires the lock, the lockdet goes active and initializes the fifo. note: pclk is held re- set when rstb is active. 3. the user can also initialize the fifo by raising phinit. during the normal running operation, the incoming data is passed from the piclk timing domain to the internally generated, divide-by-16 clock timing do- main. although the frequency of piclk and the internally generated clock is the same, their phase relationship is arbitrary. to prevent errors caused by short setup or hold times between the two timing domains, the timing generator circuitry monitors the phase relationship between piclk and the internally generated clock. when a potential setup or hold time violation is detected, the phase error goes high. when pherr conditions occur, phinit should be activated to recenter the fifo (at least 2 pclk peri- ods). this can be done by connecting pherr to phinit. when realignment occurs, up to 10 bytes of data will be lost. the user can also take in the pherr signal, process it and send an output to phinit in such a way that idle bytes are lost during the realignment process. pherr will go inactive when the realignment is complete. receiver operation the s3067 receiver chip provides the first stage of digital processing of a receive sonet sts-48/sts- 24/sts-12/sts-3/gbe/fc bit-serial stream. the bit-serial data stream is then converted into a 16-bit half-word data format. a loopback mode is provided for diagnostic loopback (transmitter to receiver). a line loopback (receiver to transmitter) is also provided. both line and local loopback modes can be active at the same time. serial-to-parallel converter the serial-to-parallel converter consists of two 16-bit registers. the first is a serial-in, parallel-out shift reg- ister, which performs the serial-to-parallel conversion clocked by the clock recovery block. on the falling edge of the poclk, the data in the parallel register is transferred to an output parallel register which drives pout[15:0]. other operating modes diagnostic loopback when the diagnostic loopback enable (dleb) input is low, a loopback from the transmitter to the re- ceiver at the serial data rate can be set up for diagnostic purposes. the differential serial output data from the transmitter is routed to the serial-to- parallel block in place of the normal data stream (rsd). tsd/tsclk outputs are active. dleb takes precedence over sdpecl and sdttl.
8 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a line loopback the line loopback circuitry selects the source of the data and clock which is output on tsd and tsclk. when the line loopback enable input (lleb) is high, it selects data and clock from the parallel-to- serial converter block. when lleb is low, it forces the output data multiplexer to select the data and clock from the rsd and rsclk inputs, and a re- ceive-to-transmit loopback can be established at the serial data rate. diagnostic loopback and line loopback can be active at the same time. loop timing in serial loop timing mode (slptime), the clock synthesizer pll of the s3067 is bypassed, and the timing of the entire transmitter section is controlled by the receive serial clock, rsclkp/n. this mode is entered by setting the slptime input to a ttl high level. in this mode, the refclkp/n input is not used, and the ratesel input is ignored for all transmit func- tions. it should be carefully noted that the internal pll continues to operate in this mode and continues as the source for the 19mck and 155mck. there- fore these signals are being used (e.g. as the reference for an external s3076 clock recovery de- vice), the refclkp/n and ratesel inputs must be properly driven. in reference loop timing mode (rlptime), the parallel clock from the receiver (poclk) is used as the reference clock to the transmitter. in this mode, the refclkp/n input is not used. the 19mck and 155mck are generated from the poclk in this op- erating mode. when operating the s3067 in rlptime mode, the 19mck and 155mck outputs should not be used as the back-up reference clock for a clock and data recovery device (s3066, s3040). when performing loopback testing (dleb), the s3067 must not be in rlptime. squelched clock operation some integrated optical receiver/clock recovery modules force their recovered serial receive clock output to the logic zero state if the optical signal is removed or reduced below a fixed threshold. this condition is accompanied by the expected deassertion of the signal detect (sd) output. the s3067 has been designed for operation with clock recovery devices that provide continuous serial clock for seamless downstream clocking in the event of optical signal loss. for operation with an optical transceiver that pro- vides the squelched clock behavior as described above, the s3067 can be operated in the squelched clock mode by activating the squelch pin. in this condition, the receive serial clock (rsclkp/n) is used for all receiver timing when the sdlvpecl/ sdttl inputs are in the active state. when the sdlvpecl/sdttl inputs are placed in the inactive state (usually by the deassertion of lockdet or sig- nal detect from the optical transceiver/clock recovery unit), the transmitter serial clock will be used to main- tain timing in the receiver section. this will allow the poclk to continue to run and the parallel outputs to flush out the last received characters and then assume the all-zero state imposed at the serial data input. it is important to note that in this mode there will be a one-time shortening or lengthening of the poclk cycle, resulting in an apparent phase shift in the poclk at the deassertion of the sd condition. an- other similar phase shift will occur when the sd condition is reasserted. in the normal operating mode, with squelch inac- tive, there will be no phase discontinuities at the poclk output during signal loss or reacquisition (assuming operation with continuous clocking from the cru device such as the amcc s3076).
9 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a table 6. s3067 transmitter pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 0 n i p 1 n i p 2 n i p 3 n i p 4 n i p 5 n i p 6 n i p 7 n i p 8 n i p 9 n i p 0 1 n i p 1 1 n i p 2 1 n i p 3 1 n i p 4 1 n i p 5 1 n i p e l g n i s d e d n e l c e p v l i2 a 3 b 2 b 3 c 1 a 2 c 1 b 2 d 3 e 1 c 2 e 3 f 2 f 1 e 1 f 3 g l e l l a r a p , k l c i p e h t o t d e n g i l a , 6 1 - y b - e d i v i d a . t u p n i a t a d l e l l a r a p o t g n i d n o p s e r r o c ( t i b t n a c i f i n g i s t s o m e h t s i ] 5 1 [ n i p . k c o l c t u p n i e h t s i ] 0 [ n i p . ) d e t t i m s n a r t t i b t s r i f e h t , d r o w m c p h c a e f o 1 t i b , d r o w m c p h c a e f o 6 1 t i b o t g n i d n o p s e r r o c ( t i b t n a c i f i n g i s t s a e l e g d e g n i s i r e h t n o d e l p m a s s i ] 0 : 5 1 [ n i p . ) d e t t i m s n a r t t i b t s a l e h t . k l c i p f o p k l c i p n k l c i p y l l a n r e t n i d e s a i b . f f i d l c e p v l i4 a 3 a e l c y c y t u d % 0 5 y l l a n i m o n , 6 1 - y b - e d i v i d a . k c o l c t u p n i l e l l a r a p o t d e s u s i k l c i p . d e n g i l a s i ] 0 : 5 1 [ n i p h c i h w o t , k c o l c t u p n i e h t n i r e t s i g e r g n i d l o h a o t n i s t u p n i n i p e h t n o a t a d e h t r e f s n a r t s e l p m a s k l c i p f o e g d e g n i s i r e h t . r e t r e v n o c l a i r e s - o t - l e l l a r a p . ] 0 : 5 1 [ n i p 1 p a c 2 p a c g o l a n ai5 r 5 t d n a r o t i c a p a c r e t l i f p o o l l a n r e t x e e h t . r o t i c a p a c r e t l i f p o o l . 6 2 e r u g i f e e s . s n i p e s e h t o t d e t c e n n o c e r a s r o t s i s e r f e r v ic di 4 c. e g a t l o v e c n e r e f e r t u p n i l c e p v l d e d n e - e l g n i s t i n i h pe l g n i s d e d n e l c e p v l i2 g. g n i m i t l a n r e t n i n g i l a e r l l i w e g d e g n i s i r . n o i t a z i l a i t i n i e s a h p p d s t n d s t . f f i d l m c o1 1 r 2 1 r , s l a n g i s m a e r t s a t a d l a i r e s l m c l a i t n e r e f f i d . a t a d l a i r e s t i m s n a r t . e l u d o m r e t t i m s n a r t l a c i t p o n a o t d e t c e n n o c y l l a m r o n p k l c s t n k l c s t . f f i d l m c o8 r 9 r d e s u e b n a c n / p k l c s t l m c l a i t n e r e f f i d . k c o l c l a i r e s t i m s n a r t d e t c e l e s e b l l i w y c n e u q e r f k c o l c s i h t . l a n g i s d s t e h t e m i t e r o t . l e s c e f d n a l e s e t a r y b p k l c p n k l c p . f f i d l c e p v l o6 c 6 b y b k c o l c t i b l a n r e t n i e h t g n i d i v i d y b d e t a r e n e g k c o l c e c n e r e f e r a n e e w t e b s r e f s n a r t e d i w - d r o w e t a n i d r o o c o t d e s u y l l a m r o n s i t i . 6 1 . e c i v e d 7 6 0 3 s e h t d n a c i g o l m a e r t s p u r r e h pe l g n i s d e d n e l c e p v l o5 ae r e h t h c i h w r o f e l c y c k l c p h c a e g n i r u d h g i h s e s l u p . r o r r e e s a h p l a n r e t n i e h t n e e w t e b n o i t a l o i v g n i m i t d l o h / p u - t e s l a i t n e t o p a s i e h t n o d e t a d p u s i r r e h p . s n i a m o d g n i m i t k l c i p d n a k c o l c e t y b . s t u p t u o k l c p e h t f o e g d e g n i l l a f
10 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a table 7. s3067 receiver pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p d s r n d s r . f f i d l m c i5 1 h 5 1 g y l l a m r o n s l a n g i s m a e r t s a t a d l a i r e s e v i e c e r l m c l a i t n e r e f f i d . e l u d o m r e v i e c e r l a c i t p o n a o t d e t c e n n o cd n a d e s a i b y l l a n r e t n i . d e t a n i m r e t l c e p v l d se l g n i s d e d n e l c e p v l i6 1 ne v i t c a . n w o d - l l u p l a n r e t n i h t i w l c e p v l . t c e t e d l a n g i s l c e p v l l c e p v l k 0 1 d e d n e - e l g n i s a . 0 c i g o l t a d l e h s i l t t d s n e h w h g i h o t e l u d o m r e v i e c e r l a c i t p o l a n r e t x e e h t y b n e v i r d e b o t t u p n i s i l c e p v l d s n e h w . r e w o p l a c i t p o d e v i e c e r f o s s o l a e t a c i d n i l l i w s n i p ) n / p d s r ( n i a t a d l a i r e s e v i e c e r e h t n o a t a d e h t , e v i t c a n i , e v i t c a s i l c e p v l d s n e h w . o r e z t n a t s n o c a o t d e c r o f y l l a n r e t n i e b n e h w . y l l a m r o n d e s s e c o r p e b l l i w s n i p n / p d s r e h t n o a t a d d a e t s n i e l u d o m r e v i e c e r l a c i t p o e h t o t d e t c e n n o c e b o t s i l t t d s t n e m e l p m i o t h g i h d e i t e b d l u o h s l c e p v l d s n e h t , l c e p v l d s f o n a t n e m e l p m i o t d e t c e n n o c n u t f e l r o , t c e t e d l a n g i s w o l e v i t c a n a . t c e t e d l a n g i s h g i h e v i t c a l t t d sl t t v li6 1 ps i l c e p v l d s n e h w h g i h e v i t c a . t c e t e d l a n g i s l t t v l t a d l e h s i l c e p v l d s n e h w w o l e v i t c a . ) 0 c i g o l ( d e t c e n n o c n u l a n r e t x e e h t y b n e v i r d e b o t t u p n i l t t v l d e d n e - e l g n i s a . 1 c i g o l l a c i t p o d e v i e c e r f o s s o l a e t a c i d n i o t e l u d o m r e v i e c e r l a c i t p o l l i w s n i p n / p d s r e h t n o a t a d e h t , e v i t c a n i s i l t t d s n e h w . r e w o p , e v i t c a s i l t t d s n e h w . o r e z t n a t s n o c a o t d e c r o f y l l a n r e t n i e b . y l l a m r o n d e s s e c o r p e b l l i w s n i p n / p d s r e h t n o a t a d p k l c s r n k l c s r . f f i d l m c i5 1 l 5 1 k n / p d s r e h t r o f t u p n i k c o l c a y l p p u s o t d e s u . k c o l c l a i r e s e v i e c e r . d e t a n i m r e t d n a d e s a i b y l l a n r e t n i . s t u p n i 0 t u o p 1 t u o p 2 t u o p 3 t u o p 4 t u o p 5 t u o p 6 t u o p 7 t u o p 8 t u o p 9 t u o p 0 1 t u o p 1 1 t u o p 2 1 t u o p 3 1 t u o p 4 1 t u o p 5 1 t u o p e l g n i s d e d n e l c e p v l o4 1 f 6 1 e 6 1 d 4 1 e 6 1 c 5 1 d 4 1 d 5 1 c 5 1 b 4 1 a 3 1 c 3 1 a 2 1 c 2 1 b 1 1 c 1 1 b k l c o p e h t o t d e n g i l a , 6 1 y b e d i v i d a , s u b t u p t u o a t a d l e l l a r a p t i b t n a c i f i n g i s t s o m e h t s i 5 1 t u o p . k c o l c t u p t u o l e l l a r a p . ) d e v i e c e r t i b t s r i f e h t , d r o w m c p h c a e f o 1 t i b o t g n i d n o p s e r r o c ( e h t n o d e t a d p u s i ] 0 : 5 1 [ t u o p . t i b t n a c i f i n g i s t s a e l e h t s i 0 t u o p . k l c o p f o e g d e g n i l l a f p k l c o p n k l c o p . f f i d l c e p v l o0 1 b 0 1 c , e l c y c y t u d % 0 5 y l l a n i m o n , 6 1 y b e d i v i d a . k c o l c t u p t u o l e l l a r a p . a t a d t u p t u o l a i r e s d r o w ] 0 : 5 1 [ t u o p o t d e n g i l a s i t a h t k c o l c t u p t u o . k l c o p f o e g d e g n i l l a f e h t n o d e t a d p u s i ] 0 : 5 1 [ t u o p f e r v oc do 4 1 bg n i w s d i m s k c a r t . e g a t l o v e c n e r e f e r l c e p v l d e d n e - e l g n i s . s u b a t a d t u p t u o l e l l a r a p f o e g a t l o v
11 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a table 8. s3067 common pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d h c l e u q sl t t v li6 1 re v i t c a s i h c l e u q s n e h w . h g i h e v i t c a . h c l e u q s k c o l c k l c s r e h t f o e c a l p n i d e s u e b l l i w k c o l c t i m s n a r t e h t , e v i t c a n i s i d s d n a . k l c s r p k l c f e r n k l c f e r y l l a n r e t n i d e s a i b . f f i d l c e p v l i2 m 3 l t i b l a n r e t n i e h t r o f e c n e r e f e r e h t s a d e s u . t u p n i k c o l c e c n e r e f e r . r e z i s e h t n y s y c n e u q e r f k c o l c b e l dl t t v li5 1 nc i t s o n g a i d s t c e l e s . w o l e v i t c a . e l b a n e k c a b p o o l c i t s o n g a i d y r a m i r p e h t s e s u e c i v e d 7 6 0 3 s e h t , h g i h s i b e l d n e h w . k c a b p o o l 7 6 0 3 s e h t , w o l n e h w . s t u p n i ) k l c s r ( k c o l c d n a ) d s r ( a t a d e h t m o r f a t a d d n a k c o l c k c a b p o o l c i t s o n g a i d e h t s e s u e c i v e d . b e l d n i e v i t c a e r a k l c s t / d s t . r e t t i m s n a r t b e l ll t t v li4 1 nn e h w . k c a b p o o l e n i l s t c e l e s . w o l e v i t c a . e l b a n e k c a b p o o l e n i l k l c s r / d s r e h t m o r f a t a d e h t e t u o r l l i w 7 6 0 3 s e h t , w o l s i b e l l . s t u p t u o k l c s t / d s t e h t o t s t u p n i k l c x r l l i kl t t v li4 1 ms i k l c x r l l i k , n o i t a r e p o l a m r o n r o f . t u p n i k c o l c e v i e c e r l l i k c i g o l a o t t u p t u o k l c o p e c r o f l l i w t i , w o l s i t u p n i s i h t n e h w . h g i h . e t a t s " 0 " e m i t p l sl t t v li1 t, h g i h n e h w . h g i h e v i t c a . t u p n i t c e l e s e m i t p o o l k c o l c l a i r e s o t n o i t c e s e v i e c e r e h t m o r f k c o l c d e r e v o c e r e h t s e l b a n e e m i t p l s . k c o l c t i m s n a r t d e z i s e h t n y s e h t f o e c a l p n i d e s u e b e m i t p l rl t t v li2 t, h g i h n e h w . h g i h e v i t c a . t u p n i t c e l e s e m i t p o o l k c o l c e c n e r e f e r e h t s a d e s u e b o t r e v i e c e r e h t m o r f k l c o p s e l b a n e e m i t p l r . r e t t i m s n a r t e h t o t t u p n i k c o l c e c n e r e f e r b t s rl t t v li5 1 pg n i r u d . w o l e v i t c a , e c i v e d e h t r o f t u p n i t e s e r . t e s e r r e t s a m . d e l b a s i d e r a s k c o l c l l a , t e s e r n e t s e tl t t v li2 nl a m r o n r o f w o l . g n i t s e t n o i t c u d o r p r o f d e s u . e l b a n e t s e t . n o i t a r e p o p k c m 5 5 1 n k c m 5 5 1 . f f i d l c e p v l o4 1 r 5 1 t o c v ? t u p t u o s i h t . r e z i s e h t n y s k c o l c e h t m o r f t u p t u o k c o l c 6 1 y b l a n r e t x e e h t f o t u p n i k c o l c e c n e r e f e r e h t o t d e t c e n n o c e b d l u o h s d e d n e m m o c e r s i t i . ) 6 6 0 3 s e h t s a h c u s ( n o i t c n u f y r e v o c e r k c o l c . d e s u t o n n e h w c c v o t n / p k c m 5 5 1 e i t o t k c m 9 1e l g n i s d e d n e l c e p v l o4 1 po c v ? s i h t . r e z i s e h t n y s k c o l c e h t m o r f t u p t u o k c o l c 8 2 1 y b e h t f o t u p n i k c o l c e c n e r e f e r e h t o t d e t c e n n o c e b d l u o h s t u p t u o k c m 9 1 e i t o t d e d n e m m o c e r s i t i . n o i t c n u f y r e v o c e r k c o l c l a n r e t x e . d e s u t o n n e h w c c v o t t e d k c o ll t t v lo1 ho t d e k c o l s a h l l p e h t r e t f a e v i t c a s e o g . h g i h e v i t c a . t c e t e d k c o l n a s i t e d k c o l . s n i p k l c f e r e h t n o d e d i v o r p k c o l c e h t . t u p t u o s u o n o r h c n y s a
12 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a table 8. s3067 common pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 0 l e s e t a r 1 l e s e t a r l t t v li 2 r 3 p ) . 2 e l b a t e e s ( . e d o m g n i t a r e p o e h t s t c e l e s . t c e l e s e t a r p k l c s s a p y b n k l c s s a p y b l a i t n e r e f f i d l m c i2 k 2 j g n i s s a p y b k c o l c l a i r e s e v i t a n r e t l a n a s e d i v o r p . k c o l c s s a p y b . o c v l a n r e t n i e h t s s a p y bl t t v li 3 mo c v e h t d n a k c o l c s s a p y b n e e w t e b s t c e l e s . h g i h e v i t c a . k c o l c ] 0 : 2 [ l e s c e fl t t v li 3 n , 2 p , 1 r. y t i l i b a p a c g n i t c e r r r o c r o r r e e h t s t c e l e s . t c e l e s c e f ) . 3 e l b a t e e s ( d n g ad n g, 4 r , 5 p , 4 p 6 t , 6 r ) v 0 ( d n u o r g c c v av 3 . 3 +4 t , 3 t , 6 py l p p u s r e w o p w o p l c e p v lv 3 . 3 +, 2 1 a , 0 1 a , 6 a , 1 d , 4 1 c , 4 b , 1 j , 4 1 g , 5 1 e , 1 n , 4 1 l , 3 k , 0 1 p , 9 p , 8 p 5 1 r , 2 1 p y l p p u s r e w o p d n g l c e p v ld n g, 3 1 b , 5 b , 1 1 a , 3 d , 5 c , 6 1 b , 1 g , 6 1 f , 5 1 f , 3 j , 4 1 h , 2 h , 7 p , 1 m , 4 1 k 4 1 t , 7 r ) v 0 ( d n u o r g w o p e r o cv 3 . 3 +, 6 1 j , 9 a , 7 a 3 1 p , 2 l y l p p u s r e w o p d n g e r o cd n g, 6 1 k , 8 b , 8 a 3 1 t , 1 l ) v 0 ( d n u o r g w o p l t tv 3 . 3 +6 1 t , 1 py l p p u s r e w o p d n g l t td n g3 r , 5 1 m) v 0 ( d n u o r g d n g c td n g9 t , 7 t) v 0 ( d n u o r g d n g d td n g2 1 t , 0 1 r) v 0 ( d n u o r g c n, 7 b , 6 1 a , 5 1 a , 8 c , 7 c , 9 b , 6 1 g , 3 h , 9 c , 4 1 j , 6 1 h , 6 1 l , 1 k , 5 1 j , 1 1 p , 6 1 m , 0 1 t , 8 t , 3 1 r 1 1 t d e t c e n n o c t o n ..
13 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 6. s3067 pinout-bottom view a b c d e f g h j k l m n p r t 1 4 n i p6 n i p9 n i p l c e p v l w o p 3 1 n i p4 1 n i p l c e p v l d n g t e d k c o l l c e p v l w o p c n e r o c d n g l c e p v l d n g l c e p v l w o p w o p l t t2 l e s c e fe m i t p l s 2 0 n i p2 n i p5 n i p7 n i p0 1 n i p2 1 n i pt i n i h p l c e p v l d n g s s a p y b n k l c s s a p y b p k l c e r o c w o p p k l c f e rn e t s e t1 l e s c e f e t a r 0 l e s e m i t p l r 3 n k l c i p1 n i p3 n i p l c e p v l d n g 8 n i p1 1 n i p5 1 n i pc n l c e p v l d n g l c e p v l w o p n k l c f e rs s a p y b0 l e s c e f e t a r 1 l e s d n g l t tc c v a 4 p k l c i p l c e p v l w o p f e r v i d n g ad n g ac c v a 5 r r e h p l c e p v l d n g l c e p v l d n g d n g a1 p a c2 p a c 6 l c e p v l w o p n k l c pp k l c p c c v ad n g ad n g a 7 e r o c w o p c nc n l c e p v l d n g l c e p v l d n g d n g c t 8 e r o c d n g e r o c d n g c n l c e p v l w o p p k l c s tc n 9 e r o c w o p c nc n l c e p v l w o p n k l c s td n g c t 0 1 l c e p v l w o p p k l c o pn k l c o p l c e p v l w o p d n g d tc n 1 1 l c e p v l d n g 5 1 t u o p4 1 t u o p c np d s tc n 2 1 l c e p v l w o p 3 1 t u o p2 1 t u o p l c e p v l w o p n d s td n g d t 3 1 1 1 t u o p l c e p v l d n g 0 1 t u o p e r o c w o p c n e r o c d n g 4 1 9 t u o pf e r v o l c e p v l w o p 6 t u o p3 t u o p0 t u o p l c e p v l w o p l c e p v l d n g c n l c e p v l d n g l c e p v l w o p x r l l i k k l c b e l lk c m 9 1p k c m 5 5 1 l c e p v l d n g 5 1 c n8 t u o p7 t u o p5 t u o p l c e p v l w o p l c e p v l d n g n d s rp d s rc nn k l c s rp k l c s rd n g l t tb e l db t s r l c e p v l w o p n k c m 5 5 1 6 1 c n l c e p v l d n g 4 t u o p2 t u o p1 t u o p l c e p v l d n g c nc n e r o c w o p e r o c d n g c nc n v l d s l c e p l t t d sh c l e u q sw o p l t t 156 pin tbga bottom view
14 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 7. s3067 pinout-top view t r p n m l k j h g f e d c b a e m i t p l s2 l e s c e fw o p l t t l c e p v l w o p l c e p v l d n g e r o c d n g c n l c e p v l w o p t e d k c o l l c e p v l d n g 4 1 n i p3 1 n i p l c e p v l w o p 9 n i p6 n i p4 n i p 1 e m i t p l r e t a r 0 l e s 1 l e s c e fn e t s e tp k l c f e r e r o c w o p s s a p y b p k l c s s a p y b n k l c l c e p v l d n g t i n i h p2 1 n i p0 1 n i p7 n i p5 n i p2 n i p0 n i p 2 c c v ad n g l t t e t a r 1 l e s 0 l e s c e fs s a p y bn k l c f e r l c e p v l w o p l c e p v l d n g c n5 1 n i p1 1 n i p8 n i p l c e p v l d n g 3 n i p1 n i pn k l c i p 3 c c v ad n g ad n g a f e r v i l c e p v l w o p p k l c i p 4 2 p a c1 p a cd n g a l c e p v l d n g l c e p v l d n g r r e h p 5 d n g ad n g ac c v a p k l c pn k l c p l c e p v l w o p 6 d n g c t l c e p v l d n g l c e p v l d n g c nc n e r o c w o p 7 c np k l c s t l c e p v l w o p c n e r o c d n g e r o c d n g 8 d n g c tn k l c s t l c e p v l w o p c nc n e r o c w o p 9 c nd n g d t l c e p v l w o p n k l c o pp k l c o p l c e p v l w o p 0 1 c np d s tc n 4 1 t u o p5 1 t u o p l c e p v l d n g 1 1 d n g d tn d s t l c e p v l w o p 2 1 t u o p3 1 t u o p l c e p v l w o p 2 1 e r o c d n g c n e r o c w o p 0 1 t u o p l c e p v l d n g 1 1 t u o p 3 1 l c e p v l d n g p k c m 5 5 1k c m 9 1b e l l x r l l i k k l c l c e p v l w o p l c e p v l d n g c n l c e p v l d n g l c e p v l w o p 0 t u o p3 t u o p6 t u o p l c e p v l w o p f e r v o9 t u o p 4 1 n k c m 5 5 1 l c e p v l w o p b t s rb e l dd n g l t tp k l c s rn k l c s rc np d s rn d s r l c e p v l d n g l c e p v l w o p 5 t u o p7 t u o p8 t u o pc n 5 1 w o p l t th c l e u q sl t t d s v l d s l c e p c nc n e r o c d n g e r o c w o p c nc n l c e p v l d n g 1 t u o p2 t u o p4 t u o p l c e p v l d n g c n 6 1 156 pin tbga top view
15 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 8. 156 pin tbga package table 9. thermal management e c i v e dr e w o p e g a k c a p x a m q ) r i a l l i t s ( a j q c j s n o i t i d n o c 7 6 0 3 sw 5 . 2w / c ? 6 . 8 1w / c ? 1. ) c ? 0 7 o t 0 ( y l n o e s u l a i c r e m m o c 7 6 0 3 sw 5 . 2w / c ? 8 . 5 1. w o l f r i a m p f l 0 0 1 . e s u l a i r t s u d n i 7 6 0 3 sw 5 . 2w / c ? 7 5 . 4 1 d 8 7 2 s t h . ) c ? 5 8 o t 0 2 - ( e s u l a i r t s u d n i . s r e l o o c p i h c m o r f k n i s t a e h
16 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a0 2 -5 8c ? v n o e g a t l o v c c d n g o t t c e p s e r h t i w5 3 1 . 33 . 35 6 4 . 3v n i p t u p n i l c e p v l y n a n o e g a t l o vv c c 2 -v c c v n i p t u p n i l t t v l y n a n o e g a t l o v0v c c v c c i 1 5 5 46 0 6a m table 12. recommended operating conditions r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? v n o e g a t l o v c c d n g o t t c e p s e r h t i w5 . 0 -6 . 3 +v n i p t u p n i l c e p v l y n a n o e g a t l o v0v c c v t n e r r u c e c r u o s t u p t u o l c e p v l d e e p s h g i h4 2a m table 11. absolute maximum ratings table 10. performance specifications r e t e m a r a pn i mp y tx a ms t i n us n o i t i d n o c r e t n e c o c v l a n i m o n y c n e u q e r f 0 1 . 27 6 . 2z h g r e t t i j t u p t u o 8 4 - s t s t e n r e h t e t i b a g i g / 4 2 - s t s ) d e t s e t t o n ( 2 1 - s t s 3 - s t s 5 0 0 . 0 5 0 0 . 0 5 0 0 . 0 5 0 0 . 0 ) s m r ( i u t a d e r u s a e m r e t t i j t u p t u o : e t o n g n i s u e t a r g n i t a r e p o t e n o s . r e t l i f e t a i r p o r p p a . k c o l n i , r e t t i j s m r k c o l c e c n e r e f e r e c n a r e l o t y c n e u q e r f 0 0 1 -0 0 1 +m p p t e n o s t e e m o t d e r i u q e r s i 0 2 . n o i t a c i f i c e p s y c n e u q e r f t u p t u o t u p n i k c o l c e c n e r e f e r e l c y c y t u d 5 45 5% e s i r k c o l c e c n e r e f e r s e m i t l l a f d n a 5 . 1s n. e d u t i l p m a f o % 0 9 o t % 0 1 esd ratings the s3067 is rated to the following voltages based on the human body model: 1. all pins are rated above 200 v. 1. outputs unterminated.
17 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a table 13. lvttl input/output dc characteristics r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v h i e g a t l o v h g i h t u p n i0 . 2v l t t c c vv l t t c c x a m = v l i e g a t l o v w o l t u p n i0 . 08 . 0vv l t t c c x a m = i h i t n e r r u c h g i h t u p n i0 5a v n i v 4 . 2 = i l i t n e r r u c w o l t u p n i0 0 5 -a v n i v 5 . 0 = v h o e g a t l o v h g i h t u p t u o4 . 2v v c c n i m = i h o a 0 0 1 - = v l o e g a t l o v w o l t u p t u o5 . 0v v c c n i m = i ol a m 5 . 1 = table 14. internally biased differential lvpecl input dc characteristics r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v l i w o l t u p n i l c e p v l v c c 0 . 2 - v c c 4 . 1 - v v h i h g i h t u p n i l c e p v l v c c 5 2 . 1 - v c c 5 5 . 0 - v d v f f i d n i g n i w s e g a t l o v t u p n i . f f i d0 0 40 0 4 2v m. 3 1 e r u g i f e e s d v e l g n i s n i g n i w s e g a t l o v t u p n i d e d n e e l g n i s0 0 20 0 2 1v m. 3 1 e r u g i f e e s v s a i b s a i b c d t u p n i v c c 5 6 . 0 - v c c 5 . 0 - v c c 5 3 . 0 - v table 15. differential lvpecl output dc characteristics r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c d v e l g n i s t u o g n i w s e g a t l o v t u p t u o d e d n e e l g n i s0 0 50 5 9v m1 5 w v o t c c . 3 1 e r u g i f e e s . 2 C d v f f i d t u o g n i w s e g a t l o v t u p t u o . f f i d0 0 0 10 0 9 1v m1 5 w v o t c c . 3 1 e r u g i f e e s . 2 C v h o e g a t l o v h g i h t u p t u o v c c 2 . 1 - v c c 5 6 . 0 - v1 5 w v o t c c 2 C v l o e g a t l o v w o l t u p t u o v c c 5 9 . 1 - v c c 0 5 . 1 - v1 5 w v o t c c 2 C
18 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a table 16. single-ended lvpecl input dc characteristics 1 table 17. single-ended lvpecl output dc characteristics 1 s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v l i e g a t l o v w o l t u p n i l c e p v c c 0 . 2 - v c c 5 . 1 - v. c 0 2 - t a d e e t n a r a u g v l i e g a t l o v w o l t u p n i l c e p v c c 0 . 2 - v c c 1 4 4 . 1 - v. c 5 8 t a d e e t n a r a u g v h i e g a t l o v h g i h t u p n i l c e p v c c 2 . 1 - v c c 5 7 . 0 - v2 - t a d e e t n a r a u g. c 0 v h i e g a t l o v h g i h t u p n i l c e p v c c 3 2 0 . 1 - v c c 5 5 . 0 - v. c 5 8 t a d e e t n a r a u g f e r v i s a i b c d l c e p v l d e d n e - e l g n i s e g a t l o v v l i 0 8 1 + v h i 0 8 1 - v m i i f e r v i r o ft n e r r u c t u p n i m u m i x a m0 0 50 5 7a s r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v l o e g a t l o v w o l t u p t u o l c e p v c c 8 9 . 1 - v c c 3 6 . 1 - v. c 0 2 - t a d e e t n a r a u g v l o e g a t l o v w o l t u p t u o l c e p v c c 8 9 . 1 - v c c 7 5 . 1 - . c 5 8 t a d e e t n a r a u g v h o e g a t l o v h g i h t u p t u o l c e p v c c 1 . 1 - v c c 0 5 8 . 0 - v. c 0 2 - t a d e e t n a r a u g v h o e g a t l o v h g i h t u p t u o l c e p v c c 5 9 . 0 - v c c 3 7 6 . 0 - . c 5 8 t a d e e t n a r a u g f e r v o s a i b c d l c e p v l d e d n e - e l g n i s e g a t l o v v c c 6 . 1 - v c c 0 2 . 1 - v v ( h o v m 0 5 2 > n i m ) f e r v o C f e r v o (v C l o v m 0 5 2 > n i m ) i o f e r v o r o ft n e r r u c t u p t u o m u m i x a m0 0 50 5 7a 1. the amcc lvpecl inputs (v il and v ih ) are non-temperature compensated i/o which vary at 1.3 mv/ c 1. the amcc lvpecl outputs are non-temperature compensated i/o which vary at 1.3 mv/ c
19 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a table 18. cml output dc characteristics r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n un o i t i d n o c v l o ) a t a d ( e g a t l o v w o l t u p t u o l m c v c c 0 . 1 - v c c 5 6 . 0 - v0 0 1 w . e n i l o t e n i l v h o ) a t a d ( e g a t l o v h g i h t u p t u o l m c v c c 5 3 . 0 - v c c 2 . 0 - v0 0 1 w . e n i l o t e n i l d v f f i d t u o ) a t a d ( e g a t l o v l a i t n e r e f f i d t u p t u o l a i r e s l m c g n i w s 0 0 80 0 6 1v m 0 0 1 w . e n i l o t e n i l . 3 1 e r u g i f e e s d v e l g n i s t u o ) a t a d ( d e d n e - e l g n i s t u p t u o l a i r e s l m c g n i w s e g a t l o v 0 0 40 0 8v m 0 0 1 w t a e n i l o t e n i l . s p b g 5 . 2 . 3 1 e r u g i f e e s v l o ) k c o l c ( e g a t l o v w o l t u p t u o l m c v c c 5 . 1 - v c c 5 8 . 0 - v0 0 1 w . e n i l o t e n i l v h o ) k c o l c ( e g a t l o v h g i h t u p t u o l m c v c c 5 . 0 - v c c 5 2 . 0 - v0 0 1 w . e n i l o t e n i l d v f f i d t u o ) k c o l c ( e g a t l o v l a i t n e r e f f i d t u p t u o l a i r e s l m c g n i w s 0 0 80 0 8 1v m 0 0 1 w . e n i l o t e n i l . 3 1 e r u g i f e e s d v e l g n i s t u o ) k c o l c ( d e d n e - e l g n i s t u p t u o l a i r e s l m c g n i w s e g a t l o v 0 0 40 0 9v m 0 0 1 w t a e n i l o t e n i l . z h g 5 . 2 . 3 1 e r u g i f e e s table 19. cml input dc characteristics r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v l i w o l t u p n i l m cv c c 7 . 1 -v c c 6 . 0 -v v h i h g i h t u p n i l m cv c c 5 5 . 0 -v c c 5 1 . 0 -v d v f f i d n i g n i w s e g a t l o v t u p n i l a i t n e r e f f i d0 0 30 0 4 2v m. 3 1 e r u g i f e e s d v e l g n i s n i g n i w s e g a t l o v t u p n i d e d n e - e l g n i s0 5 10 0 2 1v m. 3 1 e r u g i f e e s r f f i d e c n a t s i s e r t u p n i l a i t n e r e f f i d0 80 0 10 2 1 w
20 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 9. transmitter input timing 1 figure 10. transmitter output timing 1 ts pin th pin piclkp pin[15:0] tsclkp tsd ts tsd th tsd table 20. transmitter ac timing characteristics r e t e m a r a pn o i t p i r c s e dn i mx a ms t i n u y c n e u q e r f k l c s t 7 . 2z h g y c n e u q e r f k c o l c s s a p y b 7 . 2z h g e l c y c y t u d k l c s t3 47 5% r o k l c s r . t . r . w n o i t r o t s i d e l c y c y t u d k l c s t ) s e d o m s s a p y b r o b e l l , e m i t p l s n i ( k l c s s a p y b 0 . 5% e l c y c y t u d k l c i p5 35 6% s t n i p ) 9 e r u g i f e e s ( k l c i p . t . r . w e m i t p u - t e s ] 0 : 5 1 [ n i p5 . 1s n h t n i p ) 9 e r u g i f e e s ( k l c i p . t . r . w e m i t d l o h ] 0 : 5 1 [ n i p5 . 0s n p t k l c d e r e t n e c s i o f i f e h t r e t f a t f i r d k l c i p o t k l c p 2 . 5s n s t d s t ) 9 e r u g i f e e s ( g n i s i r k l c s t . t . r . w e m i t p u - t e s d s t0 0 1s p h t d s t ) 9 e r u g i f e e s ( g n i s i r k l c s t . t . r . w e m i t d l o h d s t0 0 1s p e l c y c y t u d n / p k l c p5 45 5% notes on high-speed timing: 1. timing is measured from the cross-over point of the reference signal to the 50% level of the input/output.
21 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a table 21. ac receiver timing characteristics l o b m y sn o i t p i r c s e dn i mx a ms t i n u e l c y c y t u d k l c o p5 45 5% p t t u o p y a l e d . p o r p d i l a v ] 0 : 5 1 [ t u o p o t w o l k l c o p ) 2 1 e r u g i f e e s ( 8 . 1 -8 . 1 +s n s t t u o p ) z h g 8 8 4 . 2 C z h g 1 . 2 ( k l c o p . t . r . w e m i t p u - t e s ] 0 : 5 1 [ t u o p ) 1 1 e r u g i f e e s ( 5 2 . 2s n s t t u o p ) z h g 7 6 . 2 C 8 8 4 . 2 ( k l c o p . t . r . w e m i t p u - t e s ] 0 : 5 1 [ t u o p ) 1 1 e r u g i f e e s ( 2s n h t t u o p ) 1 1 e r u g i f e e s ( k l c o p . t . r . w e m i t d l o h ] 0 : 5 1 [ t u o p2s n s t d s r ) 1 1 e r u g i f e e s ( k l c s r . t . r . w e m i t p u - t e s d s r5 7s p h t d s r ) 1 1 e r u g i f e e s ( k l c s r . t . r . w e m i t d l o h d s r5 7s p e l c y c y t u d k l c s r0 40 6% y c n e u q e r f k l c s r 7 . 2z h g figure 12. receiver output timing diagram 1 figure 11. receiver input timing diagram 1 notes on high-speed lvpecl input timing: 1. timing is measured from the cross-over point of the reference signal to the 50% level of the output. ts rsd th rsd rsd rsclkp ts pout tp pout th pout poclkp pout[15:0] notes on high-speed lvpecl input timing: 1. timing is measured from the cross-over point of the reference signal to the 50% level of the output.
22 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 13. differential voltage measurement note: v(+) C v(-) is the algebraic difference of the input signals. figure 14. phase adjust timing 1 v(+) v(? v(+) ?v(-) 0.0v v swing v d = 2 x v swing pherr transfer clk (internal) piclkp pclkp phinit 2 byte clocks 4-10 byte clocks 1. byte clock = 155.52 mhz
23 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 16. +5v differential cml driver to s3067 differential cml input ac coupled termination figure 15. s3076 to s3067 differential cml input termination +5 v serdatop/n serclkop/n +3.3 v s3067 rsdp/n rsclkp/n 0.01 f vcc -0.5 v 0.01 f 100 vcc -0.5 v zo=50 zo=50 +3.3 v s3076 serdatop/n serclkop/n +3.3 v s3067 rsdp/n rsclkp/n vcc -0.5 v 100 vcc -0.5 v zo=50 zo=50 figure 17. single-ended lvpecl driver to s3067 single-ended lvpecl input termination +3.3 v +3.3 v 82 130 s3067 pin[15:0] phinit +3.3 v ivref zo=50 ovref 0.01 f
24 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 20. s3067 single-ended lvpecl driver to single-ended lvpecl input termination +3.3 v +3.3 v 51 s3067 vcc-2 v zo=50 0.01 f pout[15:0] pherr ovref figure 18. s3067 differential cml output to +5v pecl input ac coupled termination figure 19. s3067 single-ended lvpecl driver to single-ended lvpecl input termination +3.3 v +5 v 100 s3067 tsdp/n tsclkp/n 0.01 f 0.01 f zo=50 zo=50 +3.3 v +3.3 v 82 130 s3067 zo=50 3.3 v pout[15:0] pherr ovref 0.01 f
25 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a figure 21. s3067 single-ended lvpecl driver to differential lvpecl input termination +3.3 v +3.3 v 100 100 s3067 pout[15:0] pherr zo=50 200 0.1 f amazon s4801 figure 22. s3067 differential lvpecl driver to differential lvpecl input termination figure 23. s3067 differential lvpecl driver to differential lvpecl input termination 51 s3067 pclkp/n poclkp/n zo=50 zo=50 vcc? 51 vcc? +3.3 v +3.3 v 82 130 s3067 pclkp/n poclkp/n zo=50 zo=50 82 130 +3.3 v +3.3 v
26 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a 1 k 10 f 1 k cap1 cap2 figure 26. external loop filter components figure 24. s3067 differential lvpecl driver to differential lvpecl input termination 1 1. with 100 w line to line, v ol max increases by 100 mv . 200 s3067 pclkp/n poclkp/n zo=50 zo=50 200 100 +3.3 v +3.3 v figure 25. differential lvpecl driver to s3067 internally biased differential lvpecl inputs s3067 piclkp/n refclkp/n 100 +3.3 v +3.3 v zo=50 zo=50 v cc -0.5 v v cc -0.5 v
27 s3067 multirate (oc-48/24/12/3/gbe/fc) sonet/sdh/atm transceiver w/ fec september 17, 2002/ revision a ordering information amcc is a registered trademark of applied micro circuits corporation. copyright ? 2002 applied micro circuits corporation d476/r1608 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 x i f e r pe c i v e de g a k c a pn o i s i v e r t i u c r i c d e t a r g e t n i C s7 6 0 3a g b t 6 5 1 C b t0 2 x xxxx xx prefix part no. package revision (S3067TB20) xx

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